1. Field of the Invention
The present invention is generally related to automated embedded computer test systems and in particular to a test system implementing automated functional testing, including test case generation, execution, and result verification, of embedded processor systems.
2. Description of the Related Art
Efficient and effective testing of embedded computer systems, whether in design or manufacturing verification or in failure analysis contexts, continues to be problematic for a variety of reasons. Perhaps the foremost reason is the already substantial and continually increasing complexity and density of embedded processor systems. Other reasons include the practical consequences of variant designs and, in the extreme, designs subject to frequent and significant design revision. That is, where a base embedded system design is engineered to support multiple feature sets or where fundamentally new designs are introduced into the testing regime, the corresponding complex of testing procedures must adapt accordingly. Often, such changes require significant re-engineering of the test procedures and extensive re-validation of reference test results, both of which are often considerably time and cost-intensive.
Traditionally, testing systems implement in-circuit testing (ICT) in order to qualify the operational behavior of the components that comprise some typically board-level product. In the particular case of embedded processor-based systems, which typically include an embedded processor, on-board firmware and local memory, and associated set of highly integrated peripheral components, standard in-circuit testing approaches seek to effectively isolate each component for testing as a functional unit. Conventional in-circuit testing systems will often utilize a so-called “bed-of-nails” platform to obtain simultaneous electrical access to upwards of 7,000 discrete contact points on an embedded system circuit board. With the prevalence of multilayer boards and highly integrated components using ball-grid-array (BGA) and other hidden contact packages, as well as double-sided mounting, meaningful electrical access to individual components is often quite limited.
Where testing of individual components is not possible, related components are conventionally segregated into distinct clusters for functional testing as a unit. Traditionally, substantial engineering time is required to both identify testable clusters and, further, identify the operational dependencies of each cluster on the surrounding circuits and components. Since a cluster remains connected with its surrounding circuitry, the functional testing of the cluster must account for limitations on how the cluster can be driven without damaging other components and how output contact points within the cluster will be affected by connection to other circuitry external to the cluster.
In-circuit testing is further complicated whenever design changes occur. Any design change external to a cluster will require re-analysis of dependencies between the external and cluster internal components. Equally, any design change within a cluster, whether by alteration of an existing component or introduction of additional components will frequently require a re-analysis and identification of the testable clusters. These problems are both commonly encountered and long appreciated. U.S. Pat. No. 5,004,978, issued to Morris, Jr. et al., describes a method of automatically identifying dependency changes, due to design alterations, that will affect a given cluster. The identified dependency changes are also utilized to determine how to functionally drive the cluster and the sequencing of input signals that will exercise the function of the cluster.
Similarly, U.S. Pat. No. 5,323,108, issued to Marker, III et al., describes a method of recognizing clusters based on a pattern matching of models used to describe the interconnected collection of components within clusters. Where a design modification is made, as when a new embedded system is presented for test, different collections of components are scanned to locate best matches with generic component models previously established and stored for reference. Any remaining components are individual matched to generic models. Consequently, a significant portion of the engineering effort to identify clusters can be automated. Even so, automated identification of clusters remains time intensive and still requires specific details of the clusters and individual components to be hand edited into the specific instance set of models that describe the specific embedded system.
Boundary scan is a well-developed technology that can be used to functionally increase the available test points within an embedded system accessible for in-circuit testing (IEEE 1149.1-2001, “Test Access Port and Boundary-Scan Architecture,” available from the IEEE, 445 Hoes Lane, PO Box 1331, Piscataway, N.J. 08855-1331, USA or http://standards.ieee.org/catalog, developed by the Joint Test Access Group (JTAG)). The boundary scan standard, initially established in 1990 and subsequently revised and expanded in 2001, has been progressively adopted by different integrated circuit manufacturers. To comply with the standard, an integrated circuit device must physically include a standard-defined 4-wire test access port (TAP), internal boundary-scan cells for each pin, and associated internal boundary-scan registers and other circuitry. A boundary scan description language (BSDL) file is provided by the manufacturer to describe the boundary-scan testable device functions available for use in testing.
Conventionally, the TAP ports of the devices are connected in a serial chain that is accessible through test-point pins commonly referred to as a JTAG interface. Thus, by writing and reading test data vectors through a JTAG interface, different boundary-scan cells, each associated with some device pin, can be driven and queried as part of an in-circuit test procedure. While boundary scan test techniques can be used alone, or “fixtureless,” boundary-scan is frequently used in combination with bed-of-nail platforms to reduce the size and complexity of component clusters. Even with reduced cluster size and complexity, however, conventional test systems utilizing boundary scan techniques still require time and engineering intensive cluster identification and dependency analysis.
Traditionally, circuit and systems level testing is performed initially for design verification and, subsequently, for manufacturing verification as an integral step in the production process. Further testing will be later performed for failure analysis of products returned due to, or at least suspected, in-field failure. Often, quite different test systems are used in each context to meet the different performance and commercial requirements that exist in each context. In particular, manufacturing verification requires expedient testing to support the manufacturing run rates necessary for cost-effective production. Test speed must be balanced against thoroughness to ensure that manufacturing yields are sufficient to minimize the cost of post delivery customer support and product returns. In many cases, a yield improvement of just a few percent may determine the overall profitability of a given product. Consequently, manufacturing verification testers, particularly where the product produced is a complex embedded processor system, are conventionally dedicated, large-scale, and expensive test systems.
Consequently, there is a need for an effective and efficient test system capable of at least manufacturing verification test use and readily adaptable to implement test changes and corresponding result analysis to for new designs and incremental design variations without incurring significant time and engineering costs.